- Special Activities
The Cadence Academic Network was launched in 2007 by Cadence Europe. The aim is to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected European universities, research institutes, industry advisors and Cadence was established to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic systems. The Cadence Academic Network, therefore, significantly support and improve the universities activities.
In May 2009, Delft University of Technology has been selected as a lead university to head the Cadence Academic Network in the area of Dependability and design-for-testability. Dr. Ir. Said Hamdioui, Associate Professor at the Computer Engineering Lab of the Faculty Electrical Engineering, was invited to join The Cadence Academic Network. It is self-evident that teaching modem design of electrics systems in an efficient way and conducting research in the filed requires the use of advanced tools. This is why we are very pleased and happy to be a member of Cadence Academic Network. Thanks of the continue support of Cadence, we are able today to provide our students with the state-of-the art in design methodologies ad make them well prepared for today’s industry.
Cadence tools are an integral part of both our teaching and research activities, not only at Computer Engineering lab, but also at the electrical Engineering faculty (see links to Education and Research).
Cadence's Custom IC design tools play an important role in our practices; they give a practical understanding of our courses in developing and designing modern microelectronics systems. Examples of the used tools are Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso Spectre Circuit Simulator, Virtuoso Layout Suite, etc. We are teaching many courses where Cadence tools are used during various labs. Some of the courses are given below.
ET4293: Digital IC Design
This course will present a broad yet thorough overview of the subject of digital VLSI design, spanning both the circuit and the system abstractions. This complete picture is the only way to make the right tradeoffs, find the most suitable optimizations and the best implementation strategies for very large scale integrated circuits in deep-submicron technologies. After an introduction to technology, devices and interconnect, combinational logic gates and sequential elements are studied. This is followed by system level perspectives of implementation fabrics, interconnect issues, timing issues and the design of macro blocks. At each level, the opportunities and limitations of the physical implementation are considered for finding better solutions and tradeoffs. This includes the consequences of the analog behavior of digital systems with respect to e.g. cross-talk noise and signal waveforms, that generally tend to become more influential with each new technology generation.
The course includes a design project, using Cadence. Bonus points to be awarded for the best designs.
As system design often requires the utilization of hardware description languages we concentrate on such a language, i.e., VHDL and their associated simulation and synthesis tools. This course provides students with the background one may require in order to understand, modify, develop, and debug VHDL system designs. Covered issues are related to VHDL language constructs as well as to the utilization of simulation and synthesis tools. The addressed topics includes between others the following: hardware modeling, simulation, and synthesis; behavioral and component descriptions; signals and entities; delay models; VHDL language constructs; basic I/O; identifiers, data types, and operators.
In this course, student are required to use Cadence tools to synthesize their code during the lab assignments.
ET4351 VLSI SoC
In this course, we venture to design a system on chip, where large IP blocks are available. The design problem to be solved is how to design, connect and implement these large macro IP blocks, in the 'best' possible way, i.e. in terms of speed, bandwidth, power consumption and data reliability. Topics covered among others low power optimization and reduction techniques, Low power clock and interconnect, SoC design methodology, modelling and implementation, communication architecture and protocols. Modern design starts from a C-based description (System-C) or behaviour description through synthesis tools to an FPGA implementation. The lectures are mainly a general introduction and include a discussion and demonstration of the design tools. Early on the course, the students will start using the tools by means of a well-defined student design project that uses part (or all) of the design path. Some digital circuits (basic structures) are being studied as examples.
The aim of the course is to address 3 important aspects of Systems on Chip (SoC) design: 1) Low Power digital design issues, 2) On-chip system IP high level interconnect issues, 3) SoC design methodology issues.
Design steps include: simulation, synsthesis (DC), IO port design, power planning, clocktree generation, P&P and GDS2 (SOCE) generation.
ET4076: VLSI Test Technology & Reliability
With the continue scaling of transistor feature sizes, VLSI chip density continue increases. This results in a continue increase in the complexity VLSI technology where it has reached the point where billions of transistors are integrated on a single chip (like it is the case for System on Chip).
To guarantee the satisfaction of the customers, the produced VLSI chips have to be reliable and fully tested. Verification testing and production testing represents 50 t0 60% of the cost of making VLSI chips, and are now the biggest cost of the technology. It has been known for a while that tackling the problems associated with testing VLSI chips at earlier design stage levels significantly reduces testing cost. Thus it is important for hardware designers to be exposed to concepts of VLSI testing which can help them design better product at lower cost.
This course is an introduction to the field of digital systems testing, which is an integral part of IC design and manufacturing. The topics discussed are: Importance of VLSI Testing, Test process and Automatic Test Equipment, Defects versus Fault models, Fault simulation, Logic simulation, Combinational Circuit Testing, Sequential Circuit Testing, Memory Testing, Design-for-Testability, Scan Design, Boundary Scan, Built-in-Self Test, Delay Test, Current Testing, VLSI Reliability, etc
The main goals of the course are:
• Describe the importance of VLSI testing and reliability, its impact on the total cost and the quality of the designed product.
• Point out the strong correlation between VLSI Design and Test
• Describe the silicon/ transistor/ interconnect defect mechanisms and the way they behave at the electrical/functional level and how they are tested using fault models and test algorithms
• Define the different test methodologies for logic and sequential circuits, their advantages, disadvantages, cost, limitations, etc.
• Define the different “Design-for-Testability DFT” methodologies, their advantages, disadvantages, cost and limitations
• State the trends and challenges in VLSI Testing and Reliability
• Be able to develop test algorithms and DFT techniques for digital circuits
• Be able to better understand the “weaknesses” of digital systems and do research on VLSI Test Technology
• Become a better VLSI designer, a better test engineer/ product engineer
A new lab is developed for this course in which student use Cadence tools to be able to apply the knowledge in practice. It includes scan chains insertion, verification ofthe scan-inserted design and ATPG test generation to determine fault coverage.
Our laboratory (and our faculty) has a long-standing tradition in performing industrial and societal relevant research in a broad range of topics ranging from computer arithmetic and computer architecture to compiler construction and focusing both on embedded systems as well as high performance computing without losing sight of future and emerging technologies. In this tradition, our researchers are driven by their scientific curiosity to investigate industrial and societal relevant issues and providing solutions with a large impact. Cadence tools are used in our research activities, these include e.g., Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso Spectre Circuit Simulator, Virtuoso Layout Suite, Cadence QRC Extraction and Cadence OrCAD, etc. Some of ongoing research themes are given next.
Dependable Nano-Computing (DNC)
In this research theme, we focus on the implications of the device technologies advances on the way we design, implement, and test digital circuits and systems. In a nutshell, the DNC theme mission can be formulated as: Design and build dependable/reliable systems out of unreliable components. Within this very broad scope many research avenues have to be followed; examples are:
• Design and Test Methodologies, which focuses on all aspects related to chips quality and reliability improvement; examples are design for testability, fault tolerance, diagnosis, design for reliability, dependability, Computer-Aided Test tools, etc.
• Computation Paradigms, which deals with the development of new computing paradigms for scaled CMOS technology, but also for hybrid technologies that combine both COMS and non-CMOS technologies (e.g., nanowires) as well as for non-CMOS technologies (e.g., Single Electron Tunneling (SET), Resonant Tunneling Diodes (RTD), etc).
VLSI IC Design
The aim of this project is to model and develop hardware/software systems based on quantum devices. Particular emphases are on: (i) high-speed 2D/3D optical sensing (ii) biomedical imaging, embedded and reconfigurable processing architectures, and (iii) single-photon avalanche devices (SPAD) and design optimization techniques. A number of projects are under this research that includes:
MEGAFRAME: time-correlated systems for biophotonics and medical imaging
Gigavision: a fully digital, high dynamic range vision concept
VLSI Design and Verification
The aim of this project is to design, model and characterize VLSI systems and circuits. Particular emphases are on: (i) physical modeling and simulation of large VLSI circuits (Finite Element Methods), and (ii) superfast solvers for the resulting linear systems of equations. A number of projects are under this research that includes:
EMONIC-On-chip electromagnetic modeling
MICES: Superfast Maxwell IC Extractor and Solver
RF and High-speed Microelectronics
The aim of this project is to design and implementation of circuits for broadband and narrowband communications channels. Particular emphases are on: (i) low-cost technologies for telecommunication, and (ii) high-speed technologies for remote sensing and intelligent transportation systems. A number of projects are under this research that includes:
Design of a broadband low-noise amplifier
Design of low-power adaptive ring oscillator